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Via-In-Pad

Idea/Definition Information
Actual Project Stage: 
Implementation
Project Category: 
Lead-Free
Project Leader Company: 
Alcatel/Lucent
Background: 
  • With SnPb soldering – microvia in pad constructions (and associated small voids) have no impact on BGA thermal cycle reliability
    • The failure location is virtually always on the package side of the component, away from the small void formed above the microvia (Image 1)
  • With Pb-free SAC soldering, the failure location can be on either the component side or the board side of the solder ball (Image 2)
    • More likely with ceramic parts and waferscale parts.
    • Does the void associated with a microvia in pad negatively affect thermal cycle reliability?
  • We don’t know! – Current workaround to avoid this issue is to use filled/capped microvias
    • Cost penalty at fabrication
    • Filled microvia requirements reduce supplier base for the bare boards

(Image 1)

 

(Image 2)

Approach: 
  • Determine if void caused by microvia in pad has an effect on Pb-free solder joint reliability in BGA’s and QFN’s
  • Design and build a circuit board with components with VIP (not filled) and without.
  • ATC to failure
  • Compare results

For more information download the Via-In-Pad project proposal.

 If you would like to participate in this project please email Brian Smith.  HDP User Group Members can also sign up for this project by adding it to their preferred project list in their user profile.

HDP User Group Project Facilitator: 
Brian Smith
Key Participants: 

Alcatel-Lucent, Celestica, Cisco, Huawei, IBM, ITRI, Juniper, Meadville, Nihon Superior, Philips, Premier Semiconductors,  Sun Microsystems, Tekelec,