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Lead-Free Printed Wiring Board Material Reliability

Publication Date: 
2008
Number of Pages: 
224
Contributors: 
Alcatel-Lucent, Celestica, IBM, Sun, PWB Interconnect Solutions, Viasystems
Contributors: 

Purpose

Identify and characterize the assembly compatibility and reliability of a significant number of “lower” cost PWB materials subjected to multiple Pb-free assembly reflow cycles (6X @ 260˚C) with sufficient data to understand the reliability implications to member company use environments.

Approach: 
  • Expand data on Via Integrity to larger list of potential materials – including Far East Sources.
    • Low cost FR4’s from Far East Manufacturers
    • Limited number of High Frequency/High Speed Materials
    • A few Halogen Free Materials
  • Evaluate High Layer Count/High Resin Content Effect
    • Four board stackups:
      • 20 layer ~58% and 69%RC, .116/.118 thick
      • 6 layer, .062 thick, 48%RC,
      • 6 layer, .116 thick, 45%RC
    • Baseline – Turbo 370 and 370HR baselines on all .116 constructions
  • IST as part of test vehicle design for direct comparison of IST to Air to Air
    • Note - Acceleration factors for IST are also very high – such that a few cycle variation can affect years of field life
  • CAF PTH-PTH wall test section to evaluate the results of Pb-Free reflow on CAF performance
    • Limited to .016 hole wall to hole wall and .010 hole wall to hole wall
  • Evaluate Electrical Performance data and any effect of Pb-Free reflow on materials
  • Future Phase: Confirm/Determine Coffin Manson equation acceleration factor coefficients.
    • Requires multiple thermal cycle test conditions ($)
    • Build boards now – hold additional T/Cycling for future “phase” – budget dependent

NOTE:  This document is for Members only