Current Projects

Halogen-Free Projects

BFR/PVC Cables & Wires

HDP User Group Project Facilitator: Jack Fisher

Synopsis: A coordinated activity within the materials/cables manufacturers/ OEMs supply chain to quickly and thoroughly evaluate the phase out of BFR/PVC in wires and cables.
  Cables/Wires include:
–Internal cables/wires: SATA, ribbon…
–External cables: USB cables, wired peripheral cables (e.g. mouse, keyboard, webcams, microphones…)
–Power Cords and Power Adaptor cords

For additional information visit the BFR/PVC Cables & Wires page or contact the HDP User Group Project Facilitator listed above.

High Frequency Halogen-Free Laminate Materials

HDP User Group Project Facilitator: Jack Fisher

Synopsis: HDP User Group has run several projects evaluating standard FR-4 material, halogen free material, and lead free material. This project is a continuation of that work. We will use loW loss non-halogen free material and halogen free material in our testing. The purpose of the project however is not to publish another material evaluation, the purpose is to evaluate and characterize the test procedures

For additional information visit the High Frequency Halogen-Free Laminate Materials page or contact the HDP User Group Project Facilitator listed above.

Lead Free Projects

Lead Free Board Materials Reliability Phase 3 

HDP User Group Project Facilitator: Brian Smith

Synopsis: This project is the third phase of an initiative originally started in 2006 to assess the performance of latest generation (at the time) PWB laminate systems after being exposed to simulated Pb-Free surface mount soldering conditions.  The third phase looks at recently released materials and focuses on laminates designed for high speed applications. The project will submit selected laminate systems to an extensive mechanical and electrical integrity testing program to verify whether the materials are prone to deterioration during higher temperature soldering conditions. 

For additional information visit the Lead Free Board Materials Reliability Phase 3 page or contact the HDP User Group Project Facilitator listed above.

Lead Free Copper Erosion

HDP User Group Project Facilitator: Jack Fisher

Synopsis:  Investigate the damage to PWB wiring patterns caused by copper erosion in lead-free assembly. Copper erosion can occur during dipping, wave soldering and rework processes.

For additional information visit the Alternative Alloy Study for Hole Fill and Copper Dissolution page or contact the HDP User Group Project Facilitator listed above.

Prediction of Lead Free Solder Joint Life by Indication of Microstructure Evolution

HDP User Group Project Facilitator: Brian Smith

Synopsis: Lead free is still controversial because there is no universal acceleration model and complex factors have a significant influence on life.  So the question is: How to predict the full life if you only have a board that has worked for a few years without any failure or crack?

For additional information visit the Predict Lead free Solder Joint Life page or contact the HDP User Group Project Facilitator listed above.

SAC Aging Factors

HDP User Group Project Facilitator: Laurence Schultz

Synopsis:  HDPUG SAC Acceleration Factors Project Observation: Aging of assembled test cards at 125C for 10 days prior to ATC testing affected thermal cycle reliability.  Others are reporting varying levels of a similar phenomenon (from significant to none).

For additional information visit the SAC Aging Factors page or contact the HDP User Group Project Facilitator listed above.

Mechanical Fatigue Test Phase 2

HDP User Group Project Facilitator: Kazuhiko Nakamura

Synopsis:  

Shortening of the product development cycle requires a new method that can evaluate the reliability of solder joint in the short time instead of the conventional thermal cycle test.  There are several proposals on the solder joint reliability test using the mechanical fatigue test from universities and an institute. 

The result of this project phase 1 showed that the solder joint fatigue life by SIT’s mechanical shear fatigue test has a good correlation with conventional temperaturecycling test’s for CSP packages.  Further study will be required for other packages to substitute mechanical  fatigue tests for conventional temperature cycling test.

The objective of project phase 2 is to study the similarities and differences on fatigue life in solder jointsof leadless packages (e.g. QFN package) between conventional temperaturecycling test and mechanical fatigue tests.

For additional information visit the Mechanical Fatigue Test for Solder Joint Reliability page or contact the HDP User Group Project Facilitator listed above.

SAC Aging 2

HDP User Group Project Facilitator: Bob Smith

Synopsis:  The current HDPUG SAC Aging work using bulk solder samples showed a correlation between SAC solder properties and micro-structures with aging. The work using commercial components confirmed micro-structural changes with aging.  More work needs to be done to better understand this phenomena.

For additional information visit the SAC Aging 2 page or contact the HDP User Group Project Facilitator listed above.

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Opto Electronics Projects

Opto Interconnect

HDP User Group Project Facilitator: Jack Fisher

Synopsis:  Address performance limitations encountered in high-speed electrical backplanes (15-20+ Gbps) by use of optical signal transmission.  Demonstrate,by building a test vehicle design, that optical waveguides within a backplane can benefit the system’s interconnect topology by providing: Higher data rates, Additional I/O, and better interconnect architectures.  For additional information visit the Optoelectronics Project page or contact the HDP User Group Project Facilitator listed above.

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Power Supply Projects

Board Mount Power Supply (BMPS) Modules

HDP User Group Project Facilitator: Jack Fisher

Synopsis:  System integrators want to have well defined Lead Free requirements on Board Mount Power Supply (BMPS), Pin compatibility between functionally compliant BMPS, and industry standards for function compatibility of BMPS.  They also want to eliminate the need for modules to be attached using "press fit technology" or manual soldering.

For additional information visit the Module to PWB Interconnection page or contact the HDP User Group Project Facilitator listed above.

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 Semiconductor Packaging Projects

Advanced QFN Evaluation

HDP User Group Project Facilitator: Brian Smith

Synopsis: Key issue is how to design QFN device-, board- and solder footprint to enable easy assembly and reflow on boards assuring high solder connection yield on all pins and central pad. Focus is on relatively high pin-counts (up to 144) and separately on fine pitch (down to 0.3 mm). In addition to assembly and reliability tests, solder joint inspection methods may be elaborated.

For additional information visit the Advanced QFN Evaluation page or contact the HDP User Group Project Facilitator listed above.

3D Packaging SiP

HDP User Group Project Facilitator: Brian Smith

Synopsis: In order to multiply packaging density and improve high speed performance a SiP demonstrator will be developed, built and tested.  Solution is based on few chips embedded in organic substrate and few chips assembled on top of the same substrate.  Passives are also integrated in or on the substrate.  Outcome: Technology and electrical performance assessment.

For additional information visit the 3D Packaging SiP page or contact the HDP User Group Project Facilitator listed above.

Integrated Circuit Attachment to Printed Electronic Substrates

HDP User Group Project Facilitator: Brian Smith

Synopsis: Printed electronics is a rapidly emerging interconnect technology which utilizes conventional high volume paper printing techniques to define interconnect and passive devices on electronic flexible substrates. The technology (typically using reel to reel manufacturing processes) offers extensive cost reduction opportunities compared with standard PWB fabrication processes and opens up new markets in very low cost disposable electronics. This project will focus on the attachment of integrated circuits to printed electronic substrates to achieve a higher level of functionality . Component mounting techniques will be researched and a high volume assembly process consistent with the low cost demands for this technology will be identified and evaluated. For additional information visit the Integrated Circuit Attachment to Printed Electronic Substrates page or contact the HDP User Group Project Facilitator listed above.

Polymer Ball Interconnect

HDP User Group Project Facilitator: Brian Smith

Synopsis: Polymer balls to replace solderballs in BGAs and CSPs have been tried for many years with very different results depending on application and soldering process.  This project will look into ball manufacturers, multiple polymer compositions, coatings and soldering methods.  Reliability in drop test and thermal cycling for different size components and different amount of solder will be assessed.  Member companies representing different levels in the supply chain will together work out optimal solutions for telecom, mobile, medical and other applications.

For additional information visit the Polymer Ball Interconnect page or contact the HDP User Group Project Facilitator listed above.

Process Sensitive Components

HDP User Group Project Facilitator: Laurence Schultz

Synopsis: This project is intended to compile and publish an industry guideline document on recommended practices for the treatment of temperature sensitive components (TSC). This guideline will include inputs from IC component, non-IC component, and connector suppliers as well as OEM users and Contract Manufacturers. This document will also identify Best Practices for assembling process sensitive components, along with other component process sensitities.

For additional information visit the Process Sensitive Components page or contact the HDP User Group Project Facilitator listed above.

Anti-Counterfeit Electronics

HDP User Group Project Facilitator: Laurence Schultz

Synopsis: Counterfeit components and ingredients can and do penetrate the supply chains of all manufacturing industries, including High Density Packaging.  Standards such as SAE AS5553, SEMI T20, and ANSI-NASPO-SA-2008 are emerging to help industry address some but not all of the counterfeiting issues and concerns.  One specific important issue and concern is defining a method to combine Trace and Trace data as defined in SEMI T20 with Build of Materials (BOM) data into an “As Built” data record that would enable a meaningful Supply Chain authentication to occur.  This project will define the information to be included in such a database, and propose a format.

For additional information visit the Counterfeit Electronics page or contact the HDP User Group Project Facilitator listed above.

Printed Wiring Board Technology Projects

PWB Environmental Life Cycle Analysis

HDP User Group Project Facilitator:  Brian Smith

Synopsis: An environmental life cycle analysis study measures the CO2 emissions and energy consumption associated with the full life of a product including the impact from raw material extraction, manufacturing processes, transportation/packaging, operational life and end of life disposal. The technique is becoming increasingly recognized as an important measure for determining the impact of electrical products. This project focuses on the environmental consequences of producing and using printed wiring boards and will involve representatives from the complete PWB supply chain.

For additional information visit the PWB Environmental Life Cycle Analysis page or contact the HDP User Group Project Facilitator listed above.

Pad Cratering

HDP User Group Project Facillitator: Jack Fisher

Lead-free (LF) solder joints are stiffer than tin-lead solder joints, and LF compatible (Phenolic-cured) PCB dielectric materials are more brittle than the FR4 (dicy-cured) equivalent. These two factors, coupled with the higher peak reflow temperatures used for lead-free assemblies, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath BGA corner pads. This project will examine the phenomenon with the goal of determining test and screening methods.

For additional information visit the Pad Cratering page or contact the HDP User Group Project Facilitator listed above.

Multiple Laminations

HDP User Group Project Facillitator: Jack Fisher

The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. This project will attempt to provide statistically accurate data on multiple heat cycle stresses.

For additional information visit the Multiple Laminations page or contact the HDP User Group Project Facilitator listed above.

Emerging Technology Projects

Through Silicon Vias

HDP User Group Project Facilitator:  Brian Smith

Synopsis: Through silicon vias (TSV) offer a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck. This project (currently in the ideas stage) focuses on how TSVs can be adopted for this purpose and evaluates the challenges to applying this technology in future packaging solutions.  Possible exploration areas might include reliability of TSV interconnect, roadmapping, fabrication of high density TSV, and/or design tools.

For additional information visit the Through Silicon Vias page or contact the HDP User Group Project Facilitator listed above.