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Advanced QFN Evaluation

Idea/Definition Information
Summary: 

This project explores component footprint design and associated circuit board assembly processes for the latest generation of fine pitch QFN devices. The project will use both post assembly yield assessments and longer term reliability testing (using accelerated thermal cycling techniques) to evaluate the impact of using different design and process parameters.

If you are interested in this project and would like to subscribe to the project mailing list, please click here (members only) or email the project facilitator, Brian Smith - brians@hdpug.org.
 

Background: 

Quad Flat No (QFN) leads component packages are becoming increasingly popular, particularly for high density,small scale printed circuit board designs used in portable appliances. The packages offer low profile and space efficient solutions. However the absence of leads or solder balls combined with the very fine pitch of the terminations presents a new set of challenges for printed circuit assemblers.  Printing sufficient solder paste onto the QFN land sites and subsequent reflow of the devices without open or short circuits demands optimized guidelines for both board and stencil design. In addition paste printing parameters have to fine tuned to guarantee acceptable assembly yields.
 

Problem: 

The key objective addressed in this project is to define optimum design guidelines for QFN devices and associated PCB foot print and solder paste aperture dimensions to deliver high yielding solder connections. The focus will be on latest generation QFN package designs, including those with relatively high pin-counts (up to 164) and high density I/O incorporating both single row and multi-row formats. The project will measure the effectiveness of chosen designs by assessing both assembly yield and simulated long term reliability of the solder joints.

Approach: 

The project will underatke the following activities:

  • Conduct QFN technology roadmap and supply chain capability survey
  • Collection of assembly issues identified
  • Develop board & stencil design variables and produce DOE matrix 
  • Design, produce and assemble a test board for daisy chain QFNs
  • Conduct extensive yield analysis vs different TV design variables
  • Perform reliability testing program (Accelerated thermal cycling)
  • Perform failure analysis and identify potential follow up investigations
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